A bottleneck in microprocessor design is the use of long on-chip buses. In deep sub-micron process technology, the aspect ratio for intermediate wire layers is 2.0 or above. This indicates that as wire pitch decreases and interconnect aspect ratio increases, the lateral component of interconnect capacitance (coupling capacitance), which may be from three to five times as much as the vertical component of interconnect capacitance, will likely continue to grow so as to dominate the total interconnect capacitance of a bus. Interconnect capacitance affects bus delay and power dissipation.
In addition to capacitance effects, it has been shown that the resistance of interconnects may increase significantly when the lateral dimensions of the interconnects (width and height) are scaled to the sub-100 nanometer regime. This is due to the scattering processes of the conduction electrons at the external interfaces, e.g. interconnect surfaces, and at the internal interfaces, e.g., grain boundaries in the interconnects.
In addition to reducing the capacitance and resistance of buses, it may also be desirable to provide for a bus architecture that helps mitigate the effect of capacitance and resistance upon bus delay and power dissipation.
It has been shown that a significant savings in power (or energy) dissipation may be achieved if the number of bus lines is reduced by one-half, while keeping the same bus area and double-pumping each interconnect (serial link), e.g., multiplexing each two bits on one interconnect. This is discussed in M. Ghoneima, et al., “Serial Link Bus: A Low Power On-Chip Bus Architecture,” Proceedings of the ICCAD, November 2005. A reason for this reduction power dissipation is that if the number of bus interconnects is halved, where the same bus area is maintained, then the line pitch almost doubles. This increase in pitch allows an increase in the interconnect spacing and (or) the interconnect width, which in turn reduces the interconnect capacitance and (or) resistance. More generally, there may be a reduction in power dissipation where the number of bus lines is divided by an integer divisor, d, and the data pumping is increased by a factor equal to d, where d may be greater than two.
In order for the d-pumped bus to maintain the same throughput of the conventional parallel line bus, d bits must be transmitted within the same clock period on each interconnect. Thus, the interconnect delay of the d-pumped bus must be d times less than that of the conventional parallel-line bus. Simulations have shown that the relative reduction in serial link delay may be greater than the factor d, leading to an overall throughput increase. For example, simulations have shown that by halving the number of bus lines and double-pumping the data, the relative reduction in serial link delay is much better than 50%, and this is expected to further improve as technology scales to smaller dimensions (because CC/CG increases as technology scales). This indicates that a double-pumped serial-link with a line pitch double that of a conventional static bus may be structured to have a higher throughput. If, however, the throughput of the serial-link bus is to be kept the same as that of a conventional bus, then the extra reduction in delay (the delay slack) can be used to reduce the number of repeaters and their relative sizes. As a result, the reduction in repeater capacitance, together with the reduced serial-link capacitance, leads to an overall energy reduction when compared to a conventional static bus.
It is useful to provide a bus architecture with a further reduction in power dissipation.
The average activity factor of a line AF represents the probability that a line will switch from high to low or vice versa within a clock cycle. Each line in a conventional parallel line bus transmits one bit during each cycle, so the average activity factor of this line can vary between 0 and 1. However, as a line in a d-pumped bus serializes d bits in the same clock cycle, the average activity factor of a d-pumped line varies between 0 and d. For example, a double-pumped line will vary between 0 and 2